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| 1/13 AN1456 application note january 2002 1 evaluation board the sta304 digital audio processor is a single chip device implementing end to end digital solution for audio application. in conjunction with sta500 power bridge it gives the full digital dsp-to-power high quality chain with no need for digital-to analog converters. the sta304 evaluation kit is an example for a general application involving all the sta304 and sta500 capa- bilities, which gives the possibility to evaluate the system performances. the evaluation kit consists of two boards, and control software. in the first board an sta304 and three sta500 are available, while the second is used to connect the main board to the pc. the control software allows then to control all the evaluation board capabilities from a simple visual interface. 1.1 lpt interface (lpt300) in order to allow proper communication between the 3.3v powered (digital) evaluation board and a standard lpt interface the sta304 evaluation kit includes also the lpt interface board (lpt300) shown in figure 1. basically the interface will perform a signal level translation between 3.3v and 5v in both directions. the lpt300 interface take the supply (both 3.3v and 5v) from pins 17 and 18 of the connector j2 (see figure 2), so no regulators are on board. there is the possibility to have also the regulator on board (u3 and u4), but in that case the pins 17 and 18 should be disconnected from the sta304 evaluation board. in figure 2 the com- ponents that are not needed for lpt300 (such as regulators) are drawn in dashed lines. important: the lpt300 interface can have some problems if the pc lpt port is configured as "bi-direction- al". in order to perform a quick test, after the lpt300 is connected to the sta304 board, switch on the supply and try the "test procedure" (see the setup section). if the test doesn't succeed, try to check the pc parallel port settings: most pc in fact, can configure their lpt interface in different modes (spp/epp/ecp) and it could happen that some of those configurations are not well suited to control our evaluation kit. figure 1. lpt300 interface layout - jp1, jp3 open without u3 and u4. supply from j2 connector (default for lpt300). by luca molinari sta304 + sta500 digital audio processor evaluation board operating manual
AN1456 application note 2/13 figure 2. lpt300 interface schematic scl sda pwdn ac97_mode reset pwrdn thwarn left thwarn right thwarn lfe 3/13 AN1456 application note 1.2 sta304 evaluation board the sta304 evaluation board layout is shown in figure 3. the board has one spdif input (differential, electrical single ended, and optical), and two serial inputs. three serial output are available, as well as five analog power outputs. ac97 signals are available on connector j2 for an ac97 application (an ac97 external controller is needed). figure 3. sta304 eval. board layout spdif electrical professional (differential) spdif electrical consumer (single-end) spdif optical spdif interface selector lpt300 connector ac97 connector 5.0v 3.3v supply serial interface i/o clock input (remove the crystal before using) AN1456 application note 4/13 three power stages (sta500) are mounted on board. the three devices take the analog supply from the termi- nal j1 (10v up to 35v), as well as the digital supply from the ic6 regulator. ic3 and ic4 are configured to drive 8 ohm load (up to 30 w) on left,right,s-left,s-right, while ic1 is configured to drive 4 ohm load (up to 60 w) on lfe. some board behaviours are selectable from the jumper and the switch on board, read carefully the "setup" sec- tion to avoid board damages. before using the sta304 demo board, the jumper j4 and j5 must be shorted. this jumper could be used to perform current measurement for sta304; in fact, they are in series to all the digital (j4) and the analog (j5) sta304 supply. in case of sta500 damage, it is possible to break the supply to the damaged device using the relative jumper on the lower side of the board (near j1). be sure that all the jumpers should be shorted if you want to use all the three power chip. 6 channels application suggestions for the 6 channels applications, like dts and ac3 it is mandatory to use two sta304. in order to obtain the best results in terms of audio quality, we suggest to drive each sta50x with two pwm signals coming from a single sta304, otherwise some overlap of the pwm frames could generate undesired noise. one possible configuration is: left / right / surround l / surround r from the first sta304, centre and lfe from the second one. if sta50x in mono configuration is used for lfe (4 w application), than this lfe can be fed from any of the two sta304 because no crosstalk is present. 5/13 AN1456 application note figure 4. for the sta304 evaluation board schematic 12 10 16 14 vdd scki lrcki sdi2 sdi1 ckout scko sdo3 sdo2 sdo1 lrcko reset vcc power lfe n.m. n.m. s-left s-right 5-6-7-8 right left n.m. ac97 mode test mode sa pwdn sleft-b left-a left-b right-a right-b sright-a sright-b th_war-2 th_war-3 th_war-1 lfe-b lfe-a th_war-3 pwdn sright-b sleft-a sleft-b pwdn th_war-2 sleft-a sright-a left-a right-a right-b pwrdn pwrdn left-b pwrdn pwrdn th_war-1 pwrdn lfe-b lfe-a +3.3 +3.3 +3.3 +5v +3.3v +3.3 +5v +3.3v +3.3v vcca +3.3 vcc +5v +5v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3 +3.3v vcc vcca j12 j10 j9 j8 j11 ic2 sta300 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 sdi1/sdata_out sdi2/sdata_in lrcki/sync bcki/bit_clk vdd1 gnd1 reset ac97_mode sda scl sa test_mode vdd2 xti xto gnd2 vcc rxp rxn vss lfe_b lfe_a sright_b sright_a gnd3 vdd3 right_b right_a left_b left_a gnd4 vdd4 sleft_b sleft_a eapd lrcko sdo1 sdo2 sdo3 scko gnd5 vdd5 ckout pwdn j4 j5 j7 c8 100nf j3 j6 j2 1 2 3 4 5 6 7 8 9 10 c21 100nf l11 l12 + c68 10uf 16v c73 100nf c32 100nf c42 100nf c44 100nf c45 100nf l6 t1 1 5 2 6 r29 100 c58 100nf c38 100nf j20 r26 smd0 q1 6.144mhz 1 2 r25 1m c56 18pf c57 18pf j17 rx178a 1 2 3 data gnd +vs j18 sw2-1 13 4 3 15 2 1 sw2-2 9 8 7 11 6 5 j23 1 2 tp8 tp9 tp1 c49 100nf c72 100nf ic6 ld1086dt33 in gnd out c71 100nf c70 100nf ic5 ld1086dt50 in gnd out + c67 10uf 16v + c66 10uf 16v + c65 10uf 16v j21 2 1 3 sw1 c25 1nf r9 10k j1 1 2 c10 220nf c11 1uf r4 10k l1 10uh r5 10k r6 0 r2 202 c15 100nf l2 10uh r1 2.2 c14 100nf c3 220nf c17 100nf c9 1uf tp3 + c5 1000uf 35v r7 0 c4 100nf c6 220nf c2 1uf c12 220nf c7 680pf j13 1 2 j15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 r12 10k c26 100nf c40 100nf c30 1uf c33 100nf l4 22uh c37 470nf l5 22uh tp5 r17 0 c41 100nf c20 330pf j16 1 2 c29 100nf c27 100nf r13 6 tp6 r8 6 c34 330pf r14 10k c16 100nf l7 22uh tp7 r18 0 c23 470nf l3 22uh c19 100nf c31 100nf r16 22 c36 100nf j14 1 2 r15 6 r10 6 tp4 r19 10k r22 10k r20 10k sw3 1 2 3 4 12 11 10 9 r21 10k r36 0 tp12 c48 330pf c47 100nf tp13 tp10 c69 470nf c55 100nf r32 10k l9 22uh r27 6 c64 100nf c51 470nf r28 22 ic4 sta500 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 gnd-sub out2b out2b vcc2b gnd2b gnd2a vcc2a out2a out2a out1b out1b vcc1b gnd1b gnd1a vcc1a out1a out1a n.c. gnd-clean gnd-reg vdd vdd ibias config pwrdn tri-state fault th_war in1a in1b in2a in2b vss vss vccsign. vccsign. c74 100nf c52 100nf c59 1uf j22 1 2 r30 10k c62 330pf r35 0 j19 1 2 r33 6 c75 100nf l13 22uh c76 100nf c61 100nf l8 22uh + c50 470uf 35v r31 6 c77 100nf c46 100nf c60 100nf tp11 c54 1uf c53 100nf r34 22 r23 6 jp4 jp5 lf1 1 2 3 c4a 100nf + c1 2200uf 35v c28 1uf ic1 sta500 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 gnd-sub out2b out2b vcc2b gnd2b gnd2a vcc2a out2a out2a out1b out1b vcc1b gnd1b gnd1a vcc1a out1a out1a n.c. gnd-clean gnd-reg vdd vdd ibias config pwrdn tri-state fault th_war in1a in1b in2a in2b vss vss vccsign. vccsign. r24 75 c39 100nf c43 100nf c24 100nf ic3 sta500 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 gnd-sub out2b out2b vcc2b gnd2b gnd2a vcc2a out2a out2a out1b out1b vcc1b gnd1b gnd1a vcc1a out1a out1a n.c. gnd-clean gnd-reg vdd vdd ibias config pwrdn tri-state fault th_war in1a in1b in2a in2b vss vss vccsign. vccsign. tp2 c27a 100nf c18 100nf c53a 100nf l10 22uh r3 22 r3a 22 r11 22 + c50a 470uf 35v AN1456 application note 6/13 1.3 setup and configuration before connecting the lpt300 and sta304 boards, check the jumper configuration: the sw3 switch should be configured in this way: n ac97 "on" (switch 1) n test_mode "off" (switch 2) n sa "off" (switch 3) n pwdn "on" (switch 4) it is mandatory that the second switch is off, otherwise the sta304 is set to test mode. to avoid board damages the switch 1 and 4 should not be off when the lpt interface is connected. the sec- ond switch set the sa pin, so the i2c address can be changed. up to now the demo board software can use only the seven bit address 0x1e (011110), so sa should be off. now the lpt300 interface and the sta304 demo board could be plugged together (be careful, see figure 5 for the plug). connect the pc parallel port to the lpt board using a parallel cable, and turn on the board supply. run sta304.exe on the pc, and select the register page. push the "reset" button. in this condition the board should waste about 150-200ma. try now the "test" button, the software should read the first four, and the last four registers via i2c. if the val- ues read are equal to the default the "pass" message should appear, and the i2c interface is working. if the test fail, try first of all to check the pc configuration. try to change the parallel port configuration (epp, ecp, etc.) and retry the test procedure starting from the reset. if the test is still fail, check the supply on the lpt interface, and on the sta304 demo board. try to check also if the i2c signals (scl, sda) are moving while the test button is pressed. if sda or scl are not moving, may- be the lpt interface could be damaged. figure 5. to select the spdif input way, the switch sw2 must be configured: the numbers in the first column mean that a slider in the sw2 switch must be put in that position: for example 2-4-6-8 means that a slider must be in position 2, an other in position 4, an other in position 6, and the last in position 8. when the electrical professional interface is selected, it is mandatory that the sta304 be configured as spdif sw2 config. selected interface 2-4-6-8 electrical professional 1-3-6-8 electrical consumer 1-3-5-7 optical component side component side sta300 evaluation board lpt300 7/13 AN1456 application note analog (i/o page in the control panel) . for the other interfaces, both analog and digital could be used depend- ing on input spdif levels. spdif digital could be used only if the rxp signal is in the range 0.2*vdd for vil, and 0.8*vdd for vih. spdif analog could be used if the input spdif signal is above 400 mv peak to peak. 1.4 ddx output to activate the five ddx outputs the following procedure must be used: C select the input interface (the presets 1, 2 ,3 could be used) from i/o page; C select st table in main page; C remove the mute in the main page (*); C remove the ddx reset in main page; C push turn on in main page. at this point sound should exit from the sta500. (*) to avoid potential malfunctionings, it is recommended to remove the ddx mute only when both src and spdif are locked, i.e.: - if spdif is used, the first two bits of 77h address must be: bit 0 = 0, bit 1 = 0. - if i2s is used, the first two bits of 77h address must be bit 0 = 0, bit 1 = dont care because it is referred to spdif. 2 control software in order to control and evaluate the sta304 board a dedicated control panel has been developed. it runs on win95/98 operating system and allows complete dsp control (volume, mute, tone, etc.), full serial and spdif configuration, and demo board status monitoring (thermal warning, spdif and sample rate converter lock). 2.1 main page 1) the "controls" section groups the volume, mute and tone controls for the sta304 demo board. there is a master mute that automatically check all the mute controls, and a left/right lock that link together l-r sl- sr and cnt-lfe volume sliders. the range for the volume sliders depends on the full compliant bit in reg. 1 2 3 4 6 5 AN1456 application note 8/13 5ah (see i/o page) as described in the datasheet. 2) in this section some configuration bits are grouped (see the registers on data sheet for more info). 3) the section 3 groups the status 'led' for the board. there are 3 thermal warning (red if a sta500 goes in over heat), and two lock led for the sample rate converter (src) and for the spdif. when a thermal warning is detected, the corresponding sta500 channels will be automatically muted to avoid the part destruction (in this case a by hand power off should be suggested). all the led are updated every 300 ms. 4) some default control presets are already present in those 6 memories. to store the current control position just press down one of those buttons until it's automatically released. the presets buttons store and restore not only the volume, the tone and the mute settings, but the all registers that define the fundamental behav- iour of sta304 demo board, such as if using spdif or i2s, the ddx table, etc. (registers 0x02;0x03;0x08;0x09;0x26;0x27;0x36:0x39;0x5a:0x77). as soon as the software is started, in the memory m1,m4,m5 and m6 are stored the default sta304 settings (i.e. the reset values), while in the memory m2 there are the "spdif differential" settings, and finally in the memory m3 there are the "spdif digital". 5) use this check-box to globally enable or disable the tooltip function. 6) the "turn off/on" button is used to put in power down or resume from the power down the sta500, while the "standby/resume" button put (resume) the sta304 in (from) powerdown, leaving the i2c and ac97 in- terface alive. when entering in this page, all the controls are updated reading the sta304 registers. 2.2 i/o page in this page, all the input/output interfaces can be configured. 1) this 3 radio buttons are used to select from the 3 input interfaces supported by the sta304. 2) regarding ac97, the software controls only the full compliant bit (if checked the sta304 works in full com- pliant mode as described in the datasheet). 1 2 3 4 5 9/13 AN1456 application note 3) the serial interface has different configurations. choosing "bit clock polarity" and "lr clock polarity", the bit and word clock polarity can be changed; the 'alignment' field changes the data alignment respect to the word clock, and the number of active bit clock edges (see dap input stage section in the datasheet). 4) if 'digital input' is checked, the internal spdif trigger is bypassed, and only the rxp signal is used by sta304. in this configuration the input signal range is 0.2*vdd for vil and 0.8*vdd for vih. otherwise rxp and rxn pass through a differential schmitt trigger, and the signal should follow the aes3 specifications. 5) the output serial interface is configured in the same way of the input one (see i2s output interface section in the datasheet). when entering in this page, all the controls are updated reading the sta304 registers. 2.3 download page using this page it is possible to read and download the coefficients in sta304. it is possible also to save and load from file the values. n load: pushing the load button a load dialog will appear, and selecting a coefficients file the table 2 will be updated with the new values read. n save: pushing the save button a save dialog will appear, selecting a file name the coefficient table will be saved. n download: pushing this button the current table value will be stored in sta304. n read: pushing this button all the coefficient values will be read from sta304, and the table updated with the read values. it is possible to write a comment for the coefficients file (in box 1), and it will be saved during the save procedure, and loaded in the load procedure. 1 2 AN1456 application note 10/13 a coefficients file is made of two comment lines at the top (comments begin with '#'), and a list of pair address- value for every coefficient. note that is not mandatory to put all the coefficients in the file, but only the needed coefficient can be put. the numeric format for address and values can be either decimal or hexadecimal (ex. 0x1a). to have an example, the suggestion is to try to save the current coefficients, and to take a look to the saved file. the c code linked to the download button is: the whole coefficients table is parsed with the "for(int i" loop. a coefficient is written using the procedure de- scribed in chapter 10 of the datasheet. regarding the read button, the code is: in this case all the coefficients are read, and stored in the table m_coeff_list. the code above is just to show the read/write coefficient procedure, is not intended to show a real application code. every application could have different code. bool downloadpage::downloadcoeff() { bool result=true; char elem[8]; int val; for(int i=0;i AN1456 application note 12/13 3 cautions n leaving an sta500 output without load while this channel is playing some signal could damage the de- vice. n switch on the sta500 supply only if the sta304 is working and the button in 6 in the main page displays "turn on". n be sure that st table is selected before switch on the three sta500 4 reliable circuit design n power supply decoupling minimize inductance loop area for smd ceramic bypass capacitors configured to pins vcc1, vcc2, vccsign, vss, vdd, and ibias on sta500. poor decoupling on vcc1,2 and vccsign could generate catastrophic failures on sta500 (especially in mono configuration) during continuous full power functioning. in these conditions the devices fail to prior activating thermal warning. n power routing provide star configuration power routing to each sta500 on a multichannel amplifier. minimize induct- ance loop area between each sta500 and its respective bulk bypass capacitor. n snubber circuits locate the snubber circuits (c4+r3, c14+r8, c27+r12, c39+r17) as close as pratical between the outputs of the sta500. n output routing 1. inductor placement: maintain a minimum physical separation of one inductor's diameter, particularly be- tween inductors of different channels. 2. output traces: balance the impedance of traces in the output circuit so as to maintain source matching. match pcb traces on each output circuit to within 10 milliohms. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 13/13 AN1456 application note |
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